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Hardware Design of an RNN-based Speech Enhancement System
Hardware Design of an RNN-based Speech Enhancement System
Last Update:01.12.2024
Status: OPEN
Type: masters (short/long)
Contact: Zixiao Li (zixili@ethz.ch), Prof. Shih-Chii Liu (shih@ini.uzh.ch)
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Speech enhancement (SE) is a task to improve the input speech quality by removing the ambient background noise from the audio. While deep learning-based algorithms have provided impressive SE quality (check out two demos: RNNoise and DeepFilter), their deployment on resource-constrained edge devices is still challenging due to the high computational complexity and large size of the models. The goal of this project is to implement a complete end-to-end RNN FPGA accelerator for SE and deploy the platform for real-world demonstration.
Check out demonstrations of previous audio processing accelerators from Sensors Group here.
Prerequisite
Familiar with python, in the context of machine learning.
Familiar with Verilog or VHDL (taken VLSI I or equivalent course).
FPGA development experience is preferred, but not necessary.
Audio processing algorithms knowledge is preferred, but not necessary.
Background
[1] I. Fedorov, et al. "TinyLSTMs: Efficient Neural Speech Enhancement for Hearing Aids," Interspeech, 2020.
[2] C. Gao, et al. “EdgeDRNN: Recurrent Neural Network Accelerator for Edge Inference,” IEEE JETCAS, 2020.
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